2019
Simulating Intel/Altera FIFO IP using UVM in Questasim
In the previous post I explained a method for simulating Altera IPs in Questasim, as an example I tried to verify Altera FIFO IP using UVM in Questasim. For that, first you need to create a FIFO in Quartus II using Tools -> MegaWizard Plug-In Manager option. Instantiate a FIFO with required data width and depth. I chose data width of 8 and depth of 256 and used same clock for both read and write, which makes it synchronous.
Verifying designs with Intel/Altera IPs in Questasim
FPGA designs often contain one or more built-in IPs provided by the FPGA vendor tools. But verifying those designs is not a straight forward task. In case of Intel/Altera FPGA tools they provide their own version of Modelsim called Modelsim-Altera to simulate the designs created in Quartus Prime or Quartus II. But it is limited in what it can perform and if you want to use advanced verification techniques you will mostly want to go with Questasim.
2018
Using Microblaze softcore processor
Xilinx provides its own softcore processor IP Microblaze to use in embedded systems application. In this post and a few that follow up, I will implement the Microblaze softcore processor on Spartan 3E FPGA. After that’s done I will use Xilinx provided SDK(Software Development Kit) to write a C program to turn on LEDs using switches.
UART :: Achieving Timing closure
Although my UART project worked fine when implemented on FPGA, there are some critical warnings related to timing which shows up during the compilation.