UART

• UART receiver and transmitter is coded in SystemVerilog.
• The reciever and transmitter functionality is verified using UVM and SystemVerilog.
• The design is synthesized and implemented on Cyclone IV FPGA.
• Achieved timing closure using TimeQuest Timing Analyzer.
• Tools used: Altera Quartus II, TimeQuest and Questasim

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Design of an I²C to read data from LM75A

• Design and testbench coded in Verilog.
• Address and data cycles are as per the datasheet of LM75A.
• Design is implemented on Spartan 3E FPGA of Papilio One FPGA board.
• Temperature data is obtained in hexadecimal and displayed on seven segment display.
• Tools used: Xilinx ISE and Questasim

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8-bit RISC CPU

• The processor is coded in Verilog.
• It is simulated by initializing the memory with instructions and applying clock to the design in testbench.
• Few operations such as addition, subtraction, reading from memory to register is verified from the waveform.
• It is synthesized and implemented on Cyclone IV FPGA.
• Various internal signals are observed using SignalTap logic analyzer.
• Tools used: Intel/Altera Quartus II and Questasim

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Digital Clock on FPGA

• Design is coded in Verilog.
• Synthesized and Implemented on Spartan 3E FPGA.
• Time is displayed on the seven segment display.
• Tool used: Xilinx ISE

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